The present invention generally relates to an apparatus and the like for the design support of integrated circuits, and in particular relates to an apparatus and the like for the design support of integrated circuits capable of estimating, with high precision, the path delay at the logical design stage before the packaging design stage of the integrated circuit.
Pursuant to the high integration in semiconductor circuits, needs are arising for causing the semiconductor circuit to operate at high frequencies. In order to achieve this, it is important to design a circuit with minimal delay caused by the wiring so that the transmission of signals between gates will fall within the timing capable of following high frequencies.
Meanwhile, since the timing between gates actually becomes clear in the packaging design stage after the logical design, there are cases where the timing that was of no problem in the logical design stage cannot not be converged in the packaging design stage. In such a case, it is necessary to redo the floor plan, and in times return all the way to the functional design stage and redo the circuit design.
Thus, in order to prevent the redoing of the circuit design, it is important to set the timing with high accuracy in the logical design stage. As conventional technology there are, for example, Japanese Patent Laid-Open Publication No. 2005-352916 and Japanese Patent Laid-Open Publication No. 2006-323643.